The present invention relates, in general, to the field of integrated circuit memories. More particularly, the present invention relates to a clock generator circuit that is particularly suited to those memories in which both DDR-1 and DDR-2 modes of operation are required.
A portion of an integrated circuit memory 10 is shown in FIG. 1. Integrated circuit memory 10 includes sense amplifiers 14 (four are shown but any number is possible), data lines 16, and access devices 12 for coupling the resolved data states on the sense amplifiers 14 to the data lines 16. A “YCLK” internal clock signal is used to provide column address timing to access a particular sense amplifier as is known in the art. In FIG. 1, four separate YSELECT signals YSELECT1-YSELECT4 are shown so that each sense amplifier can be separately accessed. Each YSELECT signal is the sum of a YCLK signal and column address information.
The YCLK signal, therefore, is an internal clock associated with column address time. When YCLK is high (logic one) a sense amplifier 14 in the memory array 10 is being accessed for either read or write purposes.
The YCLK signal has traditionally been free running in prior art integrated circuit memory designs. That is, every falling edge of the main internal clock signal generated a rising YCLK edge.
The termination of the YCLK signal has had two criteria for many designs, either timer controlled, or terminated on the next rising edge of the internal clock if the timer has not expired.
In recent years, two types of memory specifications have been developed by JEDEC, namely DDR1 and DDR2. DDR1 is the first series of DOUBLE DATA RATE DRAMS specified by JEDEC. Minimum burst length is two, which implies a new random column address can be supplied every cycle, and therefore YCLK cannot be longer than one cycle. (Data is output on both edges of clock so BL2 is supported by one cycle). DDR2 is the next series of DOUBLE DATA RATE DRAMS specified by JEDEC. Minimum burst length is four, which implies a new random column address can only be supplied every other cycle, and therefore YCLK can be longer than one cycle.
A free running YCLK signal as in previous designs is not compatible with the DDR2 specification, which allows two complete cycles per read or write operation (thus one whole clock cycle can be dedicated to the YCLK instead of a half cycle). A YCLK signal that terminated on the next main clock rising is too short for DDR2 parts since again this imposes a half cycle limit. A YCLK signal that terminates past the next clock rising edge does not work for DDR1 parts since it would cause contention in the column address path.
What is desired, therefore, is a YCLK signal for an integrated circuit memory that is compatible with both DDR1 and DDR2 specifications.